4 ms·
Probably because it's both patently untrue and still informative in a way. It would be more precisely stated as "there aren't many atoms left between 5(nm) and
by 0xffff2 7y ago
Probably because it's both patently untrue and still informative in a way. It would be more precisely stated as "there aren't many atoms left between 5(nm) and 0". If my math is right, 5nm is only a width of about 25 silicon atoms.
- patrick5415 7y agoYes you would think ieee would know there are uncountably many numbers between 0 and 5.
- not2b 7y agoNo, there aren't uncountably many relevant numbers between 0 and 5, because you have to make your chip out of atoms.
- dougmwne 7y agoIEEE surely does know. I'm sure the point is to imply the marketing ridiculousness. After 1nm they'll need a new vanity metric.
- tim333 7y ago1nm is about 5 atoms so I guess the next metric would be the number of atoms. Single atom features would be kind of cool but not buildable with present technology.
- p1esk 7y agoIt is also patently untrue because "5nm" label has nothing to do with reality.
- brennanpeterson 7y agoIt isn't so far off the fin width. And practically, it isn't a terrible scaled density metric. Increasingly bad, but not terribly so. On the 5nm: it is more useful to think about scaling minima in terms of unit cells. For silicon, 5nm is about 10unit cells, where silicon behaves approximately.bulk-like (like silicon). When you make it thinner, it is statistically no longer uniform. The same logic applies everywhere: you need roghly 5nm of fin 5 nm of gate, and 5nm of space: fin pitch is limited at 20nm. For metals it is the same, but worse for resistance reasons, so pitch is limited to about 20-25nm. Gate is even worse. Even though I think all of this is sort of clearly true, there is so much room for innovation elsewhere. I. Package, stacking, memory....there are 4-5 orders of magnitude out there in power-performance. In silicon!