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Micro-ops aren't RISC. Instructions like VFMADD132PS perform a dozen of math operations, combined with RAM access, yet decode into a single micro-op.
by Const-me 7y ago
Micro-ops aren't RISC. Instructions like VFMADD132PS perform a dozen of math operations, combined with RAM access, yet decode into a single micro-op.
- acdha 7y agoNote that I wasn’t arguing that Intel had switched from one textbook architecture to another: only that it isn’t really an accurate way to discuss modern chips after decades of large teams of smart people have been borrowing each other’s ideas. As to your specific example, ARM has instructions which do complex operations as well. Does that mean it’s not a RISC CPU, or just that some engineers made a pragmatic decision to support things which are done heavily like AES or SHA?
- Const-me 7y ago> it isn’t really an accurate way to discuss modern chips I think it’s still mostly accurate, CISC/RISC is about public API i.e. instruction set. What’s inside a core is implementation details, very interesting ones and can be important for performance, but still. > ARM has instructions which do complex operations as well True, but I don’t think they combine these complex math operations with RAM access, in a single instruction?