My take is that they should use the memory subsystem to route the DMA to the appropriate L3 cache. I don't think the main issue is conserving QPI bandwidth: it

My take is that they should use the memory subsystem to route the DMA to the appropriate L3 cache. I don't think the main issue is conserving QPI bandwidth: it's minimizing latency when a core loads the data into L2. That latency often causes ~30% performance drag on e.g. packet processing applications.