3 ms·

I would point out that there _are_ consumer-grade chips with AVX-512 beyond the Xeons and Cannonlake: the Skylake-X chips such as i7-7800X, which even happen to

by pbsd 7y ago

I would point out that there _are_ consumer-grade chips with AVX-512 beyond the Xeons and Cannonlake: the Skylake-X chips such as i7-7800X, which even happen to have 2 512-bit FMA units, unlike some of the cheaper Xeons. I will point out three things that make the Sunny Cove exciting to me, beyond the obvious new instructions (based on the available slides): - There are now two ports for vector shuffles. For shuffle-heavy applications, which is often the case with bit-manipulation kernels, this is great news. This seems improved from Cannonlake. - This was already present on the Cannonlake, but integer division is drastically improved, and goes from ~30ish uops to 4. Divisions that could take up to 90 cycles will now take <=18. - There are now 4 LEA ports, up from 2, which for address calculation and small integer multiplications are quite useful.

glangdale 7y ago
"Execution port Twitter" seems divided on what the extra shuffle port will do. I'm cautiously optimistic. Integer division is never really on my radar, but yes, that's exciting. LEA is very useful, but not something I spend a huge amount of time thinking about. It would be interesting to see whether the penalty for a "slow LEA" is relaxed. You're right that the Skylake-X processors have AVX-512, but they kinda push the 'consumer' envelope. There's also no consistent branding for 'having AVX-512 or not' (they have happily adopted i7/i9 for products that don't have it). These are really obviously rebadged Xeons. Nothing against them, but it's a tiny niche.
- lukego 7y ago
  I am really enjoying this thread! Faster integer division is exciting to me, and so is the prospect of faster "slow LEAs." The other year I was able to speed up a Lua MD5 benchmark by 15% by eliminating slow-LEAs from the JIT backend. I only tracked down half of them though, so if the problem has eased that would save me tracking down the other half :). https://github.com/raptorjit/raptorjit/pull/55 https://github.com/raptorjit/raptorjit/pull/55

by pbsd 7y ago

glangdale 7y ago

"Execution port Twitter" seems divided on what the extra shuffle port will do. I'm cautiously optimistic. Integer division is never really on my radar, but yes, that's exciting. LEA is very useful, but not something I spend a huge amount of time thinking about. It would be interesting to see whether the penalty for a "slow LEA" is relaxed. You're right that the Skylake-X processors have AVX-512, but they kinda push the 'consumer' envelope. There's also no consistent branding for 'having AVX-512 or not' (they have happily adopted i7/i9 for products that don't have it). These are really obviously rebadged Xeons. Nothing against them, but it's a tiny niche.

lukego 7y ago
I am really enjoying this thread! Faster integer division is exciting to me, and so is the prospect of faster "slow LEAs." The other year I was able to speed up a Lua MD5 benchmark by 15% by eliminating slow-LEAs from the JIT backend. I only tracked down half of them though, so if the problem has eased that would save me tracking down the other half :). https://github.com/raptorjit/raptorjit/pull/55 https://github.com/raptorjit/raptorjit/pull/55