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There are rumors that AMD is not happy with TR2's memory performance as the 4 channel memory controller is the bottleneck, they are probably looking at 8 channe
by dis-sys 7y ago
There are rumors that AMD is not happy with TR2's memory performance as the 4 channel memory controller is the bottleneck, they are probably looking at 8 channel memory option for TR3. ;)
- ericd 7y agoHa well I wouldn’t complain if they did that. The higher core count TR2s have a bit of a weird performance profile because of the memory channel setup - two of the chiplets have to hop through another chiplet for memory accesses. Is that what you’re referring to?
- dis-sys 7y ago> Is that what you’re referring to? yes, they had to introduce that extra hop to workaround the fact that it has 4 less channel compared to the regular 8 channel EPYC.
- ericd 7y agoAh yeah, I think I remember reading that. That's why I ended up with the 16 core TR2. I briefly considered the EPYC, but for my uses (prepping data for a couple GPUs training models), 16 seemed like (and has been) enough.