This link gives a nice explanation of the google nn-processor aka TPU: https://cloud.google.com/blog/products/gcp/an-in-depth-look-at-googles-first-tensor-proc

This link gives a nice explanation of the google nn-processor aka TPU: https://cloud.google.com/blog/products/gcp/an-in-depth-look-at-googles-first-tensor-processing-unit-tpu https://cloud.google.com/blog/products/gcp/an-in-depth-look-... It boils down to: CPUs: 10s of cores GPUs: 1000s of cores NNs: 100000s of cores NNs have very simple cores (fused multiply-add and look-up table functions) but can run many of them in one cycle. FTA: Because general-purpose processors such as CPUs and GPUs must provide good performance across a wide range of applications, they have evolved myriad sophisticated, performance-oriented mechanisms. As a side effect, the behavior of those processors can be difficult to predict, which makes it hard to guarantee a certain latency limit on neural network inference. In contrast, TPU design is strictly minimal and deterministic as it has to run only one task at a time: neural network prediction. You can see its simplicity in the floor plan of the TPU die.