Good point on EPYC, I had assumed these would be using a different design like earlier generations, but the chiplet design makes this not only possible, but lik

Good point on EPYC, I had assumed these would be using a different design like earlier generations, but the chiplet design makes this not only possible, but likely where the best chiplets are going. I agree that 16 core will arrive this generation, but I could also see it being 6 months or so. I have also wondered if it is waiting for a second generation I/O die with an enhanced memory controller to feed the extra cores.