3 ms·

The question is whether those gates are really best used for this feature. Also, this feature might increase latency and make tens of millions programs run slow

• AstralStorm 7y ago
  It probably can be done generic enough in a cpu, reordering data layouts on the fly using some access and temporal locality tracing like done for caches. Slight memory cost. Security implications are important though, with programmer nor kernel no longer controlling memory layout. Initial stages of this are already seen in the various ways of memory interleaving for multiple banks, cores and cpus. The truly fun part would be speculative as opposed to tracing reordering...