Hopefully, it will not only boost RISC-V adoption, but also the FOSS EDA[1][2][3] tools, FPGA[4][5] and ASIC[6][7][8] design tools, various high-level languages

Hopefully, it will not only boost RISC-V adoption, but also the FOSS EDA[1][2][3] tools, FPGA[4][5] and ASIC[6][7][8] design tools, various high-level languages, and toolkits to work with hardware designs. You can also follow my idea[9] and initiative to create low-level hardware IR instead of al tools parsing or producing Verilog/VHDL. Apparently, both are a pretty bad fit for chip design, thus many high-level languages[10] were created. [1] KiCAD http://kicad-pcb.org/ http://kicad-pcb.org/ [2] Qucs https://github.com/Qucs/qucs https://github.com/Qucs/qucs [3] gEDA http://www.geda-project.org/ http://www.geda-project.org/ [4] Yosys https://github.com/YosysHQ/yosys https://github.com/YosysHQ/yosys [5] SymbiFlow https://symbiflow.github.io https://symbiflow.github.io [6] The OpenROAD https://theopenroadproject.org https://theopenroadproject.org [7] The OpenROAD https://github.com/The-OpenROAD-Project https://github.com/The-OpenROAD-Project [8] Chisel3 https://github.com/freechipsproject/chisel3 https://github.com/freechipsproject/chisel3 [9] https://github.com/SymbiFlow/ideas/issues/19 https://github.com/SymbiFlow/ideas/issues/19 [10] https://github.com/drom/awesome-hdl https://github.com/drom/awesome-hdl