3 ms·
I'm super curious in the semi technology to create 3 nm layers or beyond. There's not many processes to choose from to begin with thats scalable with adequate u
by syntaxing 7y ago
I'm super curious in the semi technology to create 3 nm layers or beyond. There's not many processes to choose from to begin with thats scalable with adequate uniformity. Do they use some sort of MBE process?!
- baybal2 7y agoRumours heard by me were of apple's tapeout on 7nm being tragically low yield in between 30 to 40% (throwing away half of the wafer,) but also that TSMC eventually got 7nm yields into sane values. New processes almost always have a yield drop, followed up by recovery, but anything below 50% is really unprecedented. Apple 12 is not that of a huge chip. It is big for a mobile SoC, but smaller than say a mainstream gaming grade GPU. I greatly doubt the use of MBE, most likely some regular kind of epitaxy + a lot of process control and swearing to get it right. MBE would've increased cycle times way too much (need for ultra deep vacuum and 0 impurities)