Also, if this doesn't need any significant storage, there is also the option of realizing it in MCML, which kills CMOS in dynamic power and signal speed, while

Also, if this doesn't need any significant storage, there is also the option of realizing it in MCML, which kills CMOS in dynamic power and signal speed, while being very inefficient for SRAM (you don't want an L1 cache or a register file as large as current generations in that technology).