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Your compiler or assembler might abstract it for you but most (basically anything smaller than an ARM Cortex-M) will have harvard architecture. Some MCU's ran r
by zaarn 8y ago
Your compiler or assembler might abstract it for you but most (basically anything smaller than an ARM Cortex-M) will have harvard architecture. Some MCU's ran run programs from RAM but IIRC they do it by loading RAM into Code Memory and then executing it, it looks like VN from the outside but isn't quite on the inside.
Harvard doesn't specify if you need an indirect access mechanism, plenty of HV computers can access their code memory fairly normally (either by using a special bit in the bus or opcode or mapping it into a unused section of normal address space). Harvard simply means that Code and Data come from a separate bus and in most cases that means separate devices.
If your MCU has two seperate specs for Flash/EEPROM as Data and Program Memory, then it's 100% Harvard. And that's basically most of them.
- RealityVoid 8y agoI am not arguing about the existence of Hardvard arch. on MCU's but rather on the fact that most of the time, RAM and ROM memory accesses happen in the same address space. For sure, the underlying HW might connect you to different buses, but on a lot of MCU's, from the programmer's perspective, the address space is a big flat area containing everything. For sure, my experience has probably tainted my outlook. I have the most experience with Renesas MCU's and for example on them, I can surely run programs straight from the RAM, and depending what you're doing, you might sometimes be forced to do so. I worked with Cortex M also, and they're flat address space too. I did check out the specs for Atmega MCU's and it seems those, as you described have different address spaces for data and code areas. What I want to say, I guess is that you can have a huge variety of options and architectural approaches for MCU's.