3 ms·
Many ARM chips have this.
by garmaine 8y ago
Many ARM chips have this.
- stcredzero 8y agoAny useful links? What are the terms I should search for?
- garmaine 8y agoIt’s called a “weak ordering memory model.” Synchronization requires explicit memory fence instructions. RISC-V, btw, supports both weak and strong memory models as an implementation choice.