2 ms·
While we're at it, how about we liberate CPUs and caches from communication between threads and cores?
by stcredzero 7y ago
While we're at it, how about we liberate CPUs and caches from communication between threads and cores?
- garmaine 7y agoMany ARM chips have this.
- stcredzero 7y agoAny useful links? What are the terms I should search for?
- garmaine 7y agoIt’s called a “weak ordering memory model.” Synchronization requires explicit memory fence instructions. RISC-V, btw, supports both weak and strong memory models as an implementation choice.