3 ms·
In the past (like around the time most programming languages were invented) memory speeds were faster than processor speeds. So all variable accesses were insta
by deRerum 7y ago
In the past (like around the time most programming languages were invented) memory speeds were faster than processor speeds. So all variable accesses were instantaneous. Languages like C did not have to worry about memory hierarchies.
If memory speed is 100ns then you would notice the memory bottleneck around the time when your processor speed is 10Mhz. This point was reached in the mid 1980s with the 286 processor. Yet through the addition of cache memory this bottleneck was hidden from most software. They continued to operate in a bubble as if they were still running on the hardware of the 1980s.
It’s a bit like life itself...we land mammals carry around bags of water under our skin and our cells are still batched in fluids as if we are still living in the environment of the oceans hundreds of millions of years ago.
Many programming languages have been invented since the 90s but as far as I know none of them explicitly model memory latency and make reference to memory hierarchies. It’s as if they still need to maintain the illusion that they are running on the hardware of the past.
(Note: I once read about a language called Sequioa developed at Stanford that explicitly modelled the memory hierarchy. I don’t know what happened to it).
- bogomipz 7y ago>"If memory speed is 100ns then you would notice the memory bottleneck around the time when your processor speed is 10Mhz." Sorry I'm not following the math there, whats the relation between 100ns and 10Mhz? Why is that the tipping point?
- VibrantClarity 7y ago1 second = 1 billion nanoseconds and 1 Mhz = 1 million times a second, so if something takes 100ns you can only do it 10 millions times per second (10Mhz).
- deRerum 7y agoA 10Mhz processor has a clock cycle of 100ns (0.1 millionths of a second). Those are just rough representative numbers I picked...any particular RAM delays would be different and the actual latency would be complicated by bus speeds and protocols etc.
- bogomipz 7y agoThanks for the explanations that math makes sense to me now. Cheers.
- deleted 7y ago[deleted]
- soup10 7y agomore of a hardware problem... if CPU's let you directly address and manage L1, L2, L3 cache memory high performance programmers would love it and languages like C++ would immediately add support.
- opportune 7y agoThere are tricks to pull chunks of memory into cache as is, no? Not that they are ideal.
- deRerum 7y agoAnyone can prefetch data into the cache, but letting programmers control cache eviction would open the door to all kinds of user errors which would kill performance.
- soup10 7y agotrue but it could also be very efficient, especially in cases where you have the exact hardware to test on like a game console