Yep, I wasn't sure how to word it (it's pretty hard to keep it short without being too wrong!). You're right that there are many many things you can do to the

Yep, I wasn't sure how to word it (it's pretty hard to keep it short without being too wrong!). You're right that there are many many things you can do to the code to influence the scheduling — like the reordering the compiler is doing — and at the end of the day that has a predictable impact on the scheduling. Don't get me wrong I love my compiler, and the fact that we can impact scheduling is why LLVM-Mca is useful in the first place. What I meant to write is that your x86 isn't some kind of mostly statically scheduled VLIW. the behavior of the hardware is only partly predictable, and even IACA has to make some tragic simplifications. Tweaking the alignment to play with fetch boundaries has an effect, vectorizing obviously does, picking a different mix of instructions can help, artificially loading a port to prevent a bad scheduling decision down the line is not always entirely stupid, etc... I feel it's important to keep in mind that the hardware scheduler keeps dynamic statistics on port usage, so in a sense it's more like a JIT than a compiler, static analysis is only an approximation. What little experience I have told me it's always a good idea to compare IACA and LLVM-Mca's predicted schedule with a real profiler's output :) (Thanks for giving some nuance, it's appreciated. I'm not actually a compiler engineer or doing low-level magic for a living, so if you see anything wrong I would love to be corrected!)