4 ms·

Llvm-mca – LLVM Machine Code Analyzer

134 points by nkurz 8y ago

tylerflick 8y ago
This looks really cool, but unfortunately has really limited arm support.
wyldfire 8y ago
> The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. Which targets does that include?
- jcranmer 8y ago
  x86(-64), ARM, AArch64 for sure. It looks like there's a few schedules going on for SystemZ, PowerPC, and Hexagon as well, but I'm not sure these are out-of-order processors.
  - classichasclass 8y ago
    Most recent POWER CPUs are out-of-order, with the notable exception of the POWER6.
- nwallin 8y ago
  https://github.com/llvm-mirror/llvm/blob/master/lib/Target/X86/X86.td#L466 https://github.com/llvm-mirror/llvm/blob/master/lib/Target/X... On x86, they have a scheduling model for most recent Intel Tock cycles going back to Sandy Lake, and AMD Piledriver, Jaguar, and Zen microarchitectures.
mooreed 8y ago
I want to really love this post. But I am not smart enough to know why it’s awesome. Anyone care to give a digest for mere mortals?
- fundamental 8y ago
  This tool helps look at very small chunks of assembly code to identify the cost via a simulated execution. Beyond that it focuses on multi-stage execution of instructions in a hardware pipeline, providing tools to show the execution as well as flag which factors would be the limiting factor for the code in question. The level of detail that it provides as well as the apparent simplicity of using the tool makes it unique (from what I've seen). Understanding where the limiting factor is can help optimize and tune small chunks of code.
- tux3 8y ago
  Oh it really is an awesome low-level tool, but it's not as complicated as it sounds! Here's my attempt at explaining it, hope this helps :) The gist of it is that your CPU loves to multitask (because that's so much faster), and if you like performance you want to maximize how many things it's doing at once at any time. You want every part of the CPU to have work on its schedule all the time so it doesn't sit idle. This shows you what the schedule for your code looks like so you can optimize it. -- In more details, this tool is going to read your code instruction by instruction, compute what kind of schedule the hardware will be able to make for executing each instruction, and tell you which circuits might be overworked or going unused. (Caveat: the CPU makes its own schedule on the fly as best as it can — this tool is just an approximation in software — but your compiler's best guess is still a pretty good guess in general!) For example (actual numbers! [0]) your CPU could have 4 "ports" (circuits) that can start doing math on integers (with their ALUs) at any instant in time, or 2 of those "ports" could also multiply floating-points numbers, but each circuit can only be given one kind of task at a time to keep things manageable. Well it turns out making a good schedule is a surprisingly hard problem, since if you send int work to the first two ports and you didn't foresee there'd be float work coming after, the first two ports will have a full schedule while the other two will be doing nothing. A better schedule could have had all four of them busy in parallel! You don't directly have a say in the schedule — the hardware does its best — but with LLVM-Mca (or Intel's IACA, which inspired it) you can write code that you know will be easy to schedule in parallel, and that's already some pretty awesome tools to have! [0]: https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler https://en.wikichip.org/wiki/intel/microarchitectures/skylak...
debatem1 8y ago
This is supported today in compiler explorer (https://godbolt.org https://godbolt.org, if you haven't played with it). Just choose a recent clang compiler and hit "add tool"->"LLVM mca".
- davidtgoldblatt 8y ago
  Example usage on some code with interesting pipelining + resource contention properties: https://godbolt.org/z/11oyav https://godbolt.org/z/11oyav (The code is from the stream vbyte repo; see https://lemire.me/blog/2017/09/27/stream-vbyte-breaking-new-speed-records-for-integer-compression/ https://lemire.me/blog/2017/09/27/stream-vbyte-breaking-new-... ). Edit: Example interesting fact: the first iteration takes 35 cycles before it finishes; but the reciprocal throughput of the loop (assuming it executes a few times) is 5.3 cycles.
d99kris 8y ago
On a related note I just found that Intel has EOL'ed their IACA recently: April 2019: Intel® Architecture Code Analyzer has reached its End Of Life. Users may want to try LLVM-MCA. This is NOT a recommendation to use LLVM-MCA nor a comment on its accuracy or usefulness. Thanks for being faithful users of Intel Architecture Code Analyzer throughout the years. We hope it was useful for you. From: https://software.intel.com/en-us/articles/intel-architecture-code-analyzer https://software.intel.com/en-us/articles/intel-architecture...
benrbray 8y ago
This is really cool! I wanted to point out this wonderful article also posted to HN today that shows how LLVM MCA can help guide low level optimizations: Article: https://pdziepak.github.io/2019/05/02/on-lists-cache-algorithms-and-microarchitecture/ https://pdziepak.github.io/2019/05/02/on-lists-cache-algorit... HN: https://news.ycombinator.com/item?id=19810618 https://news.ycombinator.com/item?id=19810618

134 points by nkurz 8y ago

This looks really cool, but unfortunately has really limited arm support.

> The tool currently works for processors with an out-of-order backend, for which there is a scheduling model available in LLVM. Which targets does that include?

jcranmer 8y ago
x86(-64), ARM, AArch64 for sure. It looks like there's a few schedules going on for SystemZ, PowerPC, and Hexagon as well, but I'm not sure these are out-of-order processors.
- classichasclass 8y ago
  Most recent POWER CPUs are out-of-order, with the notable exception of the POWER6.
nwallin 8y ago
https://github.com/llvm-mirror/llvm/blob/master/lib/Target/X86/X86.td#L466 https://github.com/llvm-mirror/llvm/blob/master/lib/Target/X... On x86, they have a scheduling model for most recent Intel Tock cycles going back to Sandy Lake, and AMD Piledriver, Jaguar, and Zen microarchitectures.

mooreed 8y ago

I want to really love this post. But I am not smart enough to know why it’s awesome. Anyone care to give a digest for mere mortals?

fundamental 8y ago
This tool helps look at very small chunks of assembly code to identify the cost via a simulated execution. Beyond that it focuses on multi-stage execution of instructions in a hardware pipeline, providing tools to show the execution as well as flag which factors would be the limiting factor for the code in question. The level of detail that it provides as well as the apparent simplicity of using the tool makes it unique (from what I've seen). Understanding where the limiting factor is can help optimize and tune small chunks of code.
tux3 8y ago
Oh it really is an awesome low-level tool, but it's not as complicated as it sounds! Here's my attempt at explaining it, hope this helps :) The gist of it is that your CPU loves to multitask (because that's so much faster), and if you like performance you want to maximize how many things it's doing at once at any time. You want every part of the CPU to have work on its schedule all the time so it doesn't sit idle. This shows you what the schedule for your code looks like so you can optimize it. -- In more details, this tool is going to read your code instruction by instruction, compute what kind of schedule the hardware will be able to make for executing each instruction, and tell you which circuits might be overworked or going unused. (Caveat: the CPU makes its own schedule on the fly as best as it can — this tool is just an approximation in software — but your compiler's best guess is still a pretty good guess in general!) For example (actual numbers! [0]) your CPU could have 4 "ports" (circuits) that can start doing math on integers (with their ALUs) at any instant in time, or 2 of those "ports" could also multiply floating-points numbers, but each circuit can only be given one kind of task at a time to keep things manageable. Well it turns out making a good schedule is a surprisingly hard problem, since if you send int work to the first two ports and you didn't foresee there'd be float work coming after, the first two ports will have a full schedule while the other two will be doing nothing. A better schedule could have had all four of them busy in parallel! You don't directly have a say in the schedule — the hardware does its best — but with LLVM-Mca (or Intel's IACA, which inspired it) you can write code that you know will be easy to schedule in parallel, and that's already some pretty awesome tools to have! [0]: https://en.wikichip.org/wiki/intel/microarchitectures/skylake_(client)#Scheduler https://en.wikichip.org/wiki/intel/microarchitectures/skylak...

debatem1 8y ago

This is supported today in compiler explorer (https://godbolt.org https://godbolt.org, if you haven't played with it). Just choose a recent clang compiler and hit "add tool"->"LLVM mca".

davidtgoldblatt 8y ago
Example usage on some code with interesting pipelining + resource contention properties: https://godbolt.org/z/11oyav https://godbolt.org/z/11oyav (The code is from the stream vbyte repo; see https://lemire.me/blog/2017/09/27/stream-vbyte-breaking-new-speed-records-for-integer-compression/ https://lemire.me/blog/2017/09/27/stream-vbyte-breaking-new-... ). Edit: Example interesting fact: the first iteration takes 35 cycles before it finishes; but the reciprocal throughput of the loop (assuming it executes a few times) is 5.3 cycles.

d99kris 8y ago

On a related note I just found that Intel has EOL'ed their IACA recently: April 2019: Intel® Architecture Code Analyzer has reached its End Of Life. Users may want to try LLVM-MCA. This is NOT a recommendation to use LLVM-MCA nor a comment on its accuracy or usefulness. Thanks for being faithful users of Intel Architecture Code Analyzer throughout the years. We hope it was useful for you. From: https://software.intel.com/en-us/articles/intel-architecture-code-analyzer https://software.intel.com/en-us/articles/intel-architecture...

benrbray 8y ago

This is really cool! I wanted to point out this wonderful article also posted to HN today that shows how LLVM MCA can help guide low level optimizations: Article: https://pdziepak.github.io/2019/05/02/on-lists-cache-algorithms-and-microarchitecture/ https://pdziepak.github.io/2019/05/02/on-lists-cache-algorit... HN: https://news.ycombinator.com/item?id=19810618 https://news.ycombinator.com/item?id=19810618