3 ms·
Ballpark latency numbers per 2048-bit modular multiplication: CPU—1100ns FPGA—66ns ASIC—1ns (expected) If you're a hardware engineer (or mathematician) inte
by justindrake 7y ago
Ballpark latency numbers per 2048-bit modular multiplication:
CPU—1100ns
FPGA—66ns
ASIC—1ns (expected)
If you're a hardware engineer (or mathematician) interested is building an ultra-low latency ASIC, please email justin@ethereum.org
Source: https://twitter.com/drakefjustin/status/1123143447551053824 https://twitter.com/drakefjustin/status/1123143447551053824
Context: https://www.youtube.com/watch?v=zqL_cMlPjOI https://www.youtube.com/watch?v=zqL_cMlPjOI