This is a plausible and knowledgeable-sounding argument; its only flaw is that it not true. The only relevant 'several hundred instructions' cache miss on a Co

This is a plausible and knowledgeable-sounding argument; its only flaw is that it not true. The only relevant 'several hundred instructions' cache miss on a Core 2 Duo is a L2 miss ("Last Level Cache" miss). The hardware pre-fetcher will pick up accesses to the data stream after the first 1-2 misses. No amount of minor local jumping around in Turbo-BM is going to affect this.