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From my knowledge, this is what I understood : This result could lead to task-specific neural networks implemented at the hardware circuit level. This is one s
by antpls 7y ago
From my knowledge, this is what I understood :
This result could lead to task-specific neural networks implemented at the hardware circuit level. This is one step further than quantization and should allow to further reduce energy consumption and accelerate inference time for some specific neural networks.
Would this be even more performant than a dedicated tensor accelerator (such as TPU) ?
- Matumio 7y agoYes from a hardware point of view, custom look-up tables are much cheaper than multipliers. On the other hand, the point seems to be to utilize the LUTs of FPGAs which are not very power-efficient because they also need to be fully programmable. In theory you could hard-code the weights of a network into an ASIC, or even just a new generic building block that is cheaper than multiplication. This would then be near impossible to beat, if anybody can be bothered to optimize for this architecture.
- taeric 7y agoI find it hard to think task specific neural networks will beat a lot of the current task specific hardware. Unlesqs you broaden the definition to a useless degree. I say this without diminishing what neural networks can and are doing. And I fully ack that I am not an authority in this. It would just surprise me.