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TSMC is already doing risk 5nm production and 3nm seems entirely viable. We won't see a 'wall' until sometime after 3nm (~2025). Depending on whom you talk to,

by mbell 7y ago

TSMC is already doing risk 5nm production and 3nm seems entirely viable. We won't see a 'wall' until sometime after 3nm (~2025). Depending on whom you talk to, 2nm and smaller process sizes are also viable. I wouldn't expect any serious shift away from silicon processes till 2030.

bogomipz 7y ago
>"TSMC is already doing risk 5nm production and 3nm seems entirely viable." What is "risk production?" Is this similar to prototyping? I'm not familiar with this term. Thanks
- leetcrew 7y ago
  maybe autocorrect of "risc"? I'm not familiar with the term as written either.
- mbell 7y ago
  It's analogous to a release candidate in software. Basically means the fab line has passed all tests and run some test chips but hasn't actually done a production run of anything yet. The risk of issues / bad yield is higher than it would be after a few million chips have been run through the fab to work out all the kinks. In practical terms it means they aren't building low cost consumer products yet, they are probably building low volume high $ parts that desperately need 5nm. They are also probably doing a bunch of IP verification runs, confirming process designs for all the building blocks that are used to build SoCs: ARM cores, memory controllers, IO controllers, etc.
  - purpleidea 7y ago
    > low volume high $ parts that desperately need 5nm What sorts of parts fit this criteria? Details would be appreciated, thanks!
    - Strom 7y ago
      Cryptocurrency mining hardware probably fits it. Not that low volume is preferred, but better performance per watt efficiency is definitely worth high $.
ksec 7y ago
And just a Note, TSMC Node Number is like one step smaller than Intel's equivalent. So TSMC 7nm DUV is roughly Intel 10nm. And to the point the OP was asking, I don't think there is a technical problem to 3nm, or even 2nm process size. Expect this year's iPhone A Series SoC to be on 7nm EUV, 5nm in 2020, 3nm in 2022, likely 2nm in 2024 / 2025. There may be a 5nm+ and 3nm+ in between those. Or as TSMC's CEO Joked, expect to see 5.5nm in the future. We don't have a technical barrier, we do have an economical / cost barrier. With every node progression near to doubling of design cost, not everyone can afford to be on leading node. [1] The extremetech article is an easy to read version of Semi Engineering [2], if we assume the number are correct ( I do think the number are little exaggerated ) $500M for 5nm. Apple will need to find a $2.5 BOM reduction per iPhone to off set that cost. Qualcomm will have to sell their chip $5 to $10 more expensive. Now if you imagine $1B for 3nm, and $2B+ for 2nm. Unless you are Apple, who can easily hike the price by another $100. For others like Qualcomm, this is going to create lots of problems unless they could spread the design cost over many more units. [1] https://www.extremetech.com/computing/272096-3nm-process-node https://www.extremetech.com/computing/272096-3nm-process-nod... [2] https://semiengineering.com/big-trouble-at-3nm/ https://semiengineering.com/big-trouble-at-3nm/

by mbell 7y ago

bogomipz 7y ago

>"TSMC is already doing risk 5nm production and 3nm seems entirely viable." What is "risk production?" Is this similar to prototyping? I'm not familiar with this term. Thanks

leetcrew 7y ago
maybe autocorrect of "risc"? I'm not familiar with the term as written either.
mbell 7y ago
It's analogous to a release candidate in software. Basically means the fab line has passed all tests and run some test chips but hasn't actually done a production run of anything yet. The risk of issues / bad yield is higher than it would be after a few million chips have been run through the fab to work out all the kinks. In practical terms it means they aren't building low cost consumer products yet, they are probably building low volume high $ parts that desperately need 5nm. They are also probably doing a bunch of IP verification runs, confirming process designs for all the building blocks that are used to build SoCs: ARM cores, memory controllers, IO controllers, etc.
- purpleidea 7y ago
  > low volume high $ parts that desperately need 5nm What sorts of parts fit this criteria? Details would be appreciated, thanks!
  - Strom 7y ago
    Cryptocurrency mining hardware probably fits it. Not that low volume is preferred, but better performance per watt efficiency is definitely worth high $.

ksec 7y ago

And just a Note, TSMC Node Number is like one step smaller than Intel's equivalent. So TSMC 7nm DUV is roughly Intel 10nm. And to the point the OP was asking, I don't think there is a technical problem to 3nm, or even 2nm process size. Expect this year's iPhone A Series SoC to be on 7nm EUV, 5nm in 2020, 3nm in 2022, likely 2nm in 2024 / 2025. There may be a 5nm+ and 3nm+ in between those. Or as TSMC's CEO Joked, expect to see 5.5nm in the future. We don't have a technical barrier, we do have an economical / cost barrier. With every node progression near to doubling of design cost, not everyone can afford to be on leading node. [1] The extremetech article is an easy to read version of Semi Engineering [2], if we assume the number are correct ( I do think the number are little exaggerated ) $500M for 5nm. Apple will need to find a $2.5 BOM reduction per iPhone to off set that cost. Qualcomm will have to sell their chip $5 to $10 more expensive. Now if you imagine $1B for 3nm, and $2B+ for 2nm. Unless you are Apple, who can easily hike the price by another $100. For others like Qualcomm, this is going to create lots of problems unless they could spread the design cost over many more units. [1] https://www.extremetech.com/computing/272096-3nm-process-node https://www.extremetech.com/computing/272096-3nm-process-nod... [2] https://semiengineering.com/big-trouble-at-3nm/ https://semiengineering.com/big-trouble-at-3nm/