4 ms·

A big problem with increasing the clock speed is that your processor still needs to wait for the DRAM to respond. Modern processors are crazy smart about prefet

A big problem with increasing the clock speed is that your processor still needs to wait for the DRAM to respond. Modern processors are crazy smart about prefetching, caching, and running instructions in parallel, but at some point Memory bandwidth and latency begin to dominate over CPU clock speed. Many players have started looking at puting multiple dies on the same substrate with high-speed interconnects to reduce memory latency and improve throughput. Those improvements could help push the usefulness of higher clocks a bit further.

neltnerb 7y ago
Is it roughly accurate to say that if your computing area operates at 10x the speed, you can do 10 cores worth of computing work with one core? That would free up a lot of die area for other things, though I don't know how to guess how much that extra space would improve the other bits. I'd kind of figure that such a technology would also speed up the RAM, but I suppose that's not true either if the underlying storage technology is too slow. But I know that's also an area of active research.
- analognoise 7y ago
  In CMOS the killer is that they consume power when switching (power ends up being a square of switching frequency). So if you switched. 10x, you'd have to somehow dissipate 100x the power. Your core might be small, but the industrial-sized refrigerator needed to cool it suddenly isn't.
  - baybal2 7y ago
    I thought recently, given how bad leakage gets at <10nm, why not to go back to RCL or TTL logic? A similar line of thinking lead to source-coupled logic being resurrected for use in high speed PHYs https://en.wikipedia.org/wiki/Current-mode_logic https://en.wikipedia.org/wiki/Current-mode_logic
  - neltnerb 7y ago
    My question had the assumption of something akin to vacuum transistors that allow high frequencies without the heat generation, but yes, I agree that the current technology won't scale by 10x without a generational shift in underlying approach away from MOSFETs.

neltnerb 7y ago

Is it roughly accurate to say that if your computing area operates at 10x the speed, you can do 10 cores worth of computing work with one core? That would free up a lot of die area for other things, though I don't know how to guess how much that extra space would improve the other bits. I'd kind of figure that such a technology would also speed up the RAM, but I suppose that's not true either if the underlying storage technology is too slow. But I know that's also an area of active research.

analognoise 7y ago
In CMOS the killer is that they consume power when switching (power ends up being a square of switching frequency). So if you switched. 10x, you'd have to somehow dissipate 100x the power. Your core might be small, but the industrial-sized refrigerator needed to cool it suddenly isn't.
- baybal2 7y ago
  I thought recently, given how bad leakage gets at <10nm, why not to go back to RCL or TTL logic? A similar line of thinking lead to source-coupled logic being resurrected for use in high speed PHYs https://en.wikipedia.org/wiki/Current-mode_logic https://en.wikipedia.org/wiki/Current-mode_logic
- neltnerb 7y ago
  My question had the assumption of something akin to vacuum transistors that allow high frequencies without the heat generation, but yes, I agree that the current technology won't scale by 10x without a generational shift in underlying approach away from MOSFETs.