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This seems to be mostly an umbrella effort, focusing (according to their home page) on the "RTL to GDSII" part of EDA. To the extent that they're successful, i
by 0815test 7y ago
This seems to be mostly an umbrella effort, focusing (according to their home page) on the "RTL to GDSII" part of EDA. To the extent that they're successful, it would be quite complementary with other efforts in open hardware design, focusing on generating RTL from very-high-level, parameterized, quasi-functional hardware descriptions. But I'm a bit skeptical about their overall goals, particularly since one key issue with modern ASIC design is the unwillingness on the part of fabs to openly share critically needed info about their design rules or other proprietary details of their design-related workflow - and there's no way that open-source software alone can resolve this. Of course I do think we can expect a few useful tools to come out of this effort, and maybe that's compelling enough.
- someguydave 7y agoIndeed, a fully-open fab is needed. It seems crazy that access to silicon fabrication is limited to a very small number of wealthy businesses.
- londons_explore 7y ago>. silicon fabrication is limited to a very small number of wealthy businesses. Doesn't seem so crazy when you realise a fab can cost upwards of $1B
- mud_dauber 7y agoI came here for exactly this question. An analog-centric fab with 8” wafer technology, perhaps $1B for a greenfield setup. A state of the art 12” wafer logic factory? Think $5B. Not sure about DRAM fabs but probably comparable.
- someguydave 7y agosure, but why isn't there a market for older process technologies that presumably would be cheaper to run?