19 ms·

The OpenROAD project on lowering ASIC costs and design times

22 points by xvilka 8y ago

xvilka 8y ago
See their GitHub repositories: https://github.com/The-OpenROAD-Project https://github.com/The-OpenROAD-Project
madengr 8y ago
This software is what Cadence will gladly charge you $1M/seat. Seems pretty ambitious to pull this off for free.
- bb88 8y ago
  Or you can see it as an opportunity. That just shows how ripe the electronics industry is ripe for disruption.
0815test 8y ago
This seems to be mostly an umbrella effort, focusing (according to their home page) on the "RTL to GDSII" part of EDA. To the extent that they're successful, it would be quite complementary with other efforts in open hardware design, focusing on generating RTL from very-high-level, parameterized, quasi-functional hardware descriptions. But I'm a bit skeptical about their overall goals, particularly since one key issue with modern ASIC design is the unwillingness on the part of fabs to openly share critically needed info about their design rules or other proprietary details of their design-related workflow - and there's no way that open-source software alone can resolve this. Of course I do think we can expect a few useful tools to come out of this effort, and maybe that's compelling enough.
- someguydave 8y ago
  Indeed, a fully-open fab is needed. It seems crazy that access to silicon fabrication is limited to a very small number of wealthy businesses.
  - londons_explore 8y ago
    >. silicon fabrication is limited to a very small number of wealthy businesses. Doesn't seem so crazy when you realise a fab can cost upwards of $1B
    - mud_dauber 8y ago
      I came here for exactly this question. An analog-centric fab with 8” wafer technology, perhaps $1B for a greenfield setup. A state of the art 12” wafer logic factory? Think $5B. Not sure about DRAM fabs but probably comparable.
    - someguydave 8y ago
      sure, but why isn't there a market for older process technologies that presumably would be cheaper to run?
runroader 8y ago
At first I was very confused what this had to do with the 4GL RAD language that been around since the early 90's. Seems like a poor choice of name for your project. https://en.wikipedia.org/wiki/OpenROAD https://en.wikipedia.org/wiki/OpenROAD
londons_explore 8y ago
I see no code repo, no IRC/discord channel, etc. Either this project is just a pipe dream of it isn't as open as its name implies.
- xvilka 8y ago
  See https://news.ycombinator.com/item?id=19733665 https://news.ycombinator.com/item?id=19733665

22 points by xvilka 8y ago

xvilka 8y ago

See their GitHub repositories: https://github.com/The-OpenROAD-Project https://github.com/The-OpenROAD-Project

madengr 8y ago

This software is what Cadence will gladly charge you $1M/seat. Seems pretty ambitious to pull this off for free.

bb88 8y ago
Or you can see it as an opportunity. That just shows how ripe the electronics industry is ripe for disruption.

0815test 8y ago

This seems to be mostly an umbrella effort, focusing (according to their home page) on the "RTL to GDSII" part of EDA. To the extent that they're successful, it would be quite complementary with other efforts in open hardware design, focusing on generating RTL from very-high-level, parameterized, quasi-functional hardware descriptions. But I'm a bit skeptical about their overall goals, particularly since one key issue with modern ASIC design is the unwillingness on the part of fabs to openly share critically needed info about their design rules or other proprietary details of their design-related workflow - and there's no way that open-source software alone can resolve this. Of course I do think we can expect a few useful tools to come out of this effort, and maybe that's compelling enough.

someguydave 8y ago
Indeed, a fully-open fab is needed. It seems crazy that access to silicon fabrication is limited to a very small number of wealthy businesses.
- londons_explore 8y ago
  >. silicon fabrication is limited to a very small number of wealthy businesses. Doesn't seem so crazy when you realise a fab can cost upwards of $1B
  - mud_dauber 8y ago
    I came here for exactly this question. An analog-centric fab with 8” wafer technology, perhaps $1B for a greenfield setup. A state of the art 12” wafer logic factory? Think $5B. Not sure about DRAM fabs but probably comparable.
  - someguydave 8y ago
    sure, but why isn't there a market for older process technologies that presumably would be cheaper to run?

runroader 8y ago

At first I was very confused what this had to do with the 4GL RAD language that been around since the early 90's. Seems like a poor choice of name for your project. https://en.wikipedia.org/wiki/OpenROAD https://en.wikipedia.org/wiki/OpenROAD

londons_explore 8y ago

I see no code repo, no IRC/discord channel, etc. Either this project is just a pipe dream of it isn't as open as its name implies.

xvilka 8y ago
See https://news.ycombinator.com/item?id=19733665 https://news.ycombinator.com/item?id=19733665