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Intel were in a sense lucky, their x86 was just about the most RISCy of the contemporary CISCs - opcodes are (almost) all one memory operand, no indirect memory
by Taniwha 8y ago
Intel were in a sense lucky, their x86 was just about the most RISCy of the contemporary CISCs - opcodes are (almost) all one memory operand, no indirect memory modes, no autoincrement modes (except for stack) etc etc which means instruction retry on things like page faults are easy because of few side effects
- ghaff 8y agoAnd they were basically able to transition to chips that were architecturally pretty much RISC while maintaining CISC compatibility. Furthermore, they did bet too much on frequency with x86 and compile-time optimization with Itanium, in part because a major partner was so focused on single thread performance. But, although AMD had some short-term success with Opteron, Intel was able to retrench and win out. It continues to have challenges in mobile and other areas but is still more successful than not.
- darkerside 8y agoVery interesting. It's lower level than my experience, so thanks for sharing.