> Isn't there a Python based dialect for that already? There's Migen (which is like Fairylog - a preprocessor/macro system for RTL) and MyHDL (which lets you w

> Isn't there a Python based dialect for that already? There's Migen (which is like Fairylog - a preprocessor/macro system for RTL) and MyHDL (which lets you write Verilog using a subset of 'synthesizable' Python).