3 ms·
I'm not sure I see the point, it turns a language that looks a lot like verilog but with lots more parentheses into verilog - why not just write verilog in the
by Taniwha 8y ago
I'm not sure I see the point, it turns a language that looks a lot like verilog but with lots more parentheses into verilog - why not just write verilog in the first place?
- neilv 8y agoThe author's stated motivations sounded plausible to me: > Fairylog is a Racket language (of course) which aims to be quite like Verilog, with less redundant syntax, Racket macros, and several additional compile-time features that Verilog seems to be lacking. > Fairylog extends Racket rather than replaces it, which means you can use all of Racket wherever you like in Fairylog code to help you generate stuff. I think there might be an additional benefit of this, to implementers of languages atop Racket, in that they can transform/generate syntax objects (essentially, ASTs with source location info) to use this language as backend, pretty easily. I suppose this might be good for rapid experimenting in developing/compiling for CPU+FPGA targets.
- sanxiyn 8y agoIt's Verilog with Racket macro! That sounds much better than Verilog with custom macro system cobbled with Perl, which is what is used in practice.
- q3k 8y agoPerl? A real comment I've seen in demo code from a vendor: always @(X) begin // add code from "PRBS_Calculator.xls" here...