5 ms·
The 6502 accesses memory on every cycle, predictably, so you can have memory that's clocked at the same rate and you're getting 100% utilization. Compare to Z80
by tom_ 8y ago
The 6502 accesses memory on every cycle, predictably, so you can have memory that's clocked at the same rate and you're getting 100% utilization. Compare to Z80 and 68000, for example, which access memory only intermittently, and not reliably at any N-cycle boundary. There's a couple of bits about this in this interview with Sophie Wilson, one of the ARM designers: https://www.computerhistory.org/collections/catalog/102746190 https://www.computerhistory.org/collections/catalog/10274619... (a good read)
I'm sure I read somewhere that the 6502's low interrupt latency was also an influence (the 8-bit Acorn stuff was IRQ-heavy, no DMA), but clearly it wasn't in the above PDF, so I've no idea where this came from :( - but this might not be 6502 influence necessarily, as the Z80's IRQ latency looks OK, maybe just a desire not to fuck it up like the 68000.
ARM SBC is like 6502 SBC, just an ADD with inverted input... so... maybe that counts?!
The 6502 influence is indeed not all that visible in the programming model or instruction set, but I don't think this is a bad thing.
- duskwuff 8y ago> The 6502 accesses memory on every cycle, predictably, so you can have memory that's clocked at the same rate and you're getting 100% utilization. On the flip side: it also means that the processor can't run any faster than memory, which is not great. Anyways, the 6502 uses a rather narrow 8-bit data bus with no cache, so instruction fetch takes up the majority of memory accesses -- in fact, I'm not sure you can get under 50% of memory accesses used for instruction fetch without pathological instruction sequences. It's incredibly inefficient by modern standards; even 68000 was an improvement in this regard.