3 ms·
> * Low latency GPU-CPU interaction via L3 cache Intel's GPUs kinda suck so I'm not sure how much performance you're going to get out of them even with the s
by microarchitect 16y ago
> * Low latency GPU-CPU interaction via L3 cache
Intel's GPUs kinda suck so I'm not sure how much performance you're going to get out of them even with the so called "low-latency" interconnect. On the AMD side, they have better GPUs, but unfortunately Ontario (and I believe Llano as well) don't even share northbridges, leave alone L3 cache.
- alecco 16y ago>> * Low latency GPU-CPU interaction via L3 cache > Intel's GPUs kinda suck so I'm not sure how much performance > you're going to get out of them even with the so called > "low-latency" interconnect Sure, Intel's GPUs are not as good. But latency and interaction with the CPU cores is the main problem at the moment for parallel programming out of corner cases like HPC or multimedia. You show animosity on Intel, this architecture has not yet been released. > On the AMD side, they have better GPUs, but unfortunately > Ontario (and I believe Llano as well) don't even share > northbridges, leave alone L3 cache. Llano is not the real deal with AMD Fusion. That will be Bulldozer and Bobcat. Everybody reports at least Bulldozer will have L3-level communication. http://www.anandtech.com/show/3865/amd-bobcat-bulldozer-hot-chips-presentations-online http://www.anandtech.com/show/3865/amd-bobcat-bulldozer-hot-... I would question AMD's gamble on OpenCL and lack of tools compared to Intel who acquired MIT's Cilk and absorbed other projects. Also I haven't seen anything close to Intel's SIMD sort algorithm yet (with regards of technical concepts, elegance, and sheer record-breaking performance.)