I don't know of a architechure that actually does this, but I suspect they're comparing a N->N->N truncating multiply with a N->N->N+1 addition that sets the ca

I don't know of a architechure that actually does this, but I suspect they're comparing a N->N->N truncating multiply with a N->N->N+1 addition that sets the carry flag. In addition to forcing the compiler to reorder test-fiddle-branch sequences in a potentially suboptimal way, you'd also introduce speculation hazards for any instructions that depend on the flags. I'd be interested to see any hardware where that's enough to make addition slower, though, since usually you can make up for it by dumping a extra (very cheap) adder into the execution system.