3 ms·
JIT != emulation. I've been watching the RISC-V J extension but it seems to be a blank space, a placeholder hoping that someone has a good idea for acceleratin
by CalChris 8y ago
JIT != emulation.
I've been watching the RISC-V J extension but it seems to be a blank space, a placeholder hoping that someone has a good idea for accelerating JITs. I don't even know what that would mean.
- monocasa 8y agoTo be fair, the Godson-3 that this thread is about emulates via a JIT.
- _chris_ 8y agoFor starters, you need a mechanism to notify other cores that their instructions have changed. That may mean requiring coherent icaches, or maybe some more explicit but simpler mechanism.
- monocasa 8y agoIf you don't go with coherent I-D caches, is that really cheaper than IPIs?