6 ms·
> x86 flag generation on arthmetic ops, an x86 like FPU and VU, and additional addressing modes. I've figured this was a good way forward for a while, glad to
by ChickeNES 8y ago
> x86 flag generation on arthmetic ops, an x86 like FPU and VU, and additional addressing modes.
I've figured this was a good way forward for a while, glad to see someone with the knowledge and access to a fab make it a reality :) I'm hoping that someone proposes a similar extension for RISC-V
Edit: Well I guess there's a J extension for JIT acceleration in development, guess I should have finished reading the comments before replying lol
- CalChris 8y agoJIT != emulation. I've been watching the RISC-V J extension but it seems to be a blank space, a placeholder hoping that someone has a good idea for accelerating JITs. I don't even know what that would mean.
- monocasa 8y agoTo be fair, the Godson-3 that this thread is about emulates via a JIT.
- _chris_ 8y agoFor starters, you need a mechanism to notify other cores that their instructions have changed. That may mean requiring coherent icaches, or maybe some more explicit but simpler mechanism.
- monocasa 8y agoIf you don't go with coherent I-D caches, is that really cheaper than IPIs?