4 ms·

>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to

>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.

Patrick-STH 8y ago
Likely is there because it requires that AMD's partners release servers in this configuration, and those servers are unreleased. In theory, something during validation could prevent it or partners could decide not to release this configuration (which are unlikely but still possible.)
bryanlarsen 8y ago
They claim to have confirmed this with AMD partners. So it's more than just speculation.
MattSteelblade 8y ago
From the article, "Over the past few weeks, we have managed to confirm with a number of AMD’s ecosystem partners that our theory is not only valid, but it is indeed what we will see." Essentially, there is significant evidence that supports their hypothesis. This is far more than mere speculation and I see no reason to assume they have fabricated (hehe) this story.
twotwotwo 8y ago
Yeah: > I did give AMD the heads-up that it would be going live just after the Cascade Lake launch. They did not sanction this article (indeed, they will not be overly excited to see it is live.) That seems to justify some doubts. PCIe 4.0 support has got to cost some die area/power, and not many PCI devices will support it at first. That might point towards starting with a mix of 3.0 and 4.0 lanes. If they did upgrade all lanes, and some devices show up, could be cool for some bandwidth-hungry GPU and/or HPC-networking use cases. Or for servers that wanted to load up on any kind of compatible device (SSDs, whatever): you can fit more 4.0 x4 than 3.0 x8 anythings in a given number of lanes. Still think we'll have to wait a gen, though.

4 ms·

>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to

by craftyguy 8y ago

>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.

Patrick-STH 8y ago
Likely is there because it requires that AMD's partners release servers in this configuration, and those servers are unreleased. In theory, something during validation could prevent it or partners could decide not to release this configuration (which are unlikely but still possible.)
bryanlarsen 8y ago
They claim to have confirmed this with AMD partners. So it's more than just speculation.
MattSteelblade 8y ago
From the article, "Over the past few weeks, we have managed to confirm with a number of AMD’s ecosystem partners that our theory is not only valid, but it is indeed what we will see." Essentially, there is significant evidence that supports their hypothesis. This is far more than mere speculation and I see no reason to assume they have fabricated (hehe) this story.
twotwotwo 8y ago
Yeah: > I did give AMD the heads-up that it would be going live just after the Cascade Lake launch. They did not sanction this article (indeed, they will not be overly excited to see it is live.) That seems to justify some doubts. PCIe 4.0 support has got to cost some die area/power, and not many PCI devices will support it at first. That might point towards starting with a mix of 3.0 and 4.0 lanes. If they did upgrade all lanes, and some devices show up, could be cool for some bandwidth-hungry GPU and/or HPC-networking use cases. Or for servers that wanted to load up on any kind of compatible device (SSDs, whatever): you can fit more 4.0 x4 than 3.0 x8 anythings in a given number of lanes. Still think we'll have to wait a gen, though.