Nice article. I would be interested in learning more about the rendering pipeline. Is anybody aware of a more detailed description? Or an online datasheet? Btw

Nice article. I would be interested in learning more about the rendering pipeline. Is anybody aware of a more detailed description? Or an online datasheet? Btw - already EDO DRAM favours reading entire memory blocks/lines. My suspicion is that the trick in increausing memory bandwidth is not only based on interleaving, but also on block transfers with on-chip caching. Especially critical for texture reads. The Voodoo is a nice example of how much execution matters. They were not the only ones to follow this path back then, but by only concentrating on the core functionality they managed to beat all others to the market without compromise. (Compare to S3 Virge, Matrox Mystique, Nvidia NV1, Tseng, NEC and many others)