I do this using cog for Verilog code. It lets me generate signal processing constants/math in the signal processing code itself, driven by a single control fil

I do this using cog for Verilog code. It lets me generate signal processing constants/math in the signal processing code itself, driven by a single control file (with, i.e. system sample rate) without having to rely on Verilog's awkward (where even available) math.