3 ms·
Well, as long as Intel does not devise a chip which chooses what to keep and what not to keep in the cache depending on the number of jumps executed and the nam
by pfortuny 8y ago
Well, as long as Intel does not devise a chip which chooses what to keep and what not to keep in the cache depending on the number of jumps executed and the name of the calling function... (just as way of example).
Also "optimized advanced heuristic multithreading" (for instance)...
Anyway: an astounding feat, to be honest.
- CodeWriter23 8y agoI was thinking the only true way to prevent side channel information disclosure is to ensure x microseconds are spent encrypting/decrypting each byte in a message and using an external timer source as a reference clock to enforce the constant time interval.
- pfortuny 8y agoYes but you have to be sure also that nothing at all remains in the cache...
- rrobukef 8y agoAnd EM characteristics are fixed.
- pfortuny 8y agoAlso, you never know what “side channel” may appear out the blue. Say, for instance, that Intel makes a chipnfor which 0’s spend less energy than 1’s in computations.