Open-Source tooling support (Yosys/NextPNR flow, Yosys formal verification flow, Verilator, IVerilog). VHDL only has GHDL. And there's a bunch of small project

Open-Source tooling support (Yosys/NextPNR flow, Yosys formal verification flow, Verilator, IVerilog). VHDL only has GHDL. And there's a bunch of small projects to translate synthesizable VHDL into Verilog (to then feed into the aforementioned tooling), but none of them are good.