Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys

Verilator is an awesome tool. I suggest if you are interested in open-source EDA this you also check out Icarus Verilog [1] - an event based Verilog sim, Yosys [2] - a Verilog synthesis tool and formal solver, and NextPNR [3] - a place-and-route tool. The set of these provide a pretty reasonable set of tools for developing hardware (that is HDL) with fully open source software! [1] - http://iverilog.icarus.com/ http://iverilog.icarus.com/ [2] - http://www.clifford.at/yosys/ http://www.clifford.at/yosys/ [3] - https://github.com/YosysHQ/nextpnr https://github.com/YosysHQ/nextpnr