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The hardware that was built for multiuser operation existed, for sure, but it lost out to up-jumped desktop CPUs that tried to paste it over the top of a single

The hardware that was built for multiuser operation existed, for sure, but it lost out to up-jumped desktop CPUs that tried to paste it over the top of a single-user core design. But more importantly, the tricks employed to get around the physical limits of straightforward speed scaling worked by going around that pasted-on layer of security.

wmf 8y ago
IBM seems to have no official statement about whether z is vulnerable to Spectre but Power7/8/9 are/were definitely affected. Fujitsu SPARC is also vulnerable but interestingly Oracle SPARC is not. If Alpha, MIPS, or PA-RISC still existed I would expect most of them to be vulnerable as well. Are there specific hardware mechanisms in "real" server processors that can provide high performance without side channels? What are they?
- nickpsecurity 8y ago
  I wouldn't trust them. One might mitigate a bit using the classic patterns against side channels: randomization and masking. I came up with an idea for randomizing execution at CPU level but the person that beat me to it patented it. Possibly something like ARINC partitioning combined with randomization plus operations similar to those that process secrets, but process fake data. One of the simplest methods, though, is focusing the leak-proofing on the barrier between partitions handling secrets and everything else (esp w/ comms capability). Then, you just make sure you have trusted, hard-to-hack code on as much of the system as possible. No web browsers and such. Safe, system language with pointer and overflow protections along with performance hit that comes with. Otherwise, back to physical separation. I used that with KVM switch back in the day.
- int_19h 8y ago
  MIPS still exists, it's not uncommon in cheap routers. Here's their statement on vulnerabilities: https://www.mips.com/blog/mips-response-on-speculative-execution-and-side-channel-vulnerabilities/ https://www.mips.com/blog/mips-response-on-speculative-execu...
  - rbanffy 8y ago
    In order to be vulnerable to Spectre, it needs out of order speculative execution. Not many low end CPUs do that.
- rbanffy 8y ago
  > high performance without side channels? What are they? One I can think of is cache partitioning by process id and security context. Not sure any CPU implements that. We can also use cpusets to assign processes to physical cores or sockets, limiting how much opportunity you have to see what other processes are doing. This can even increase performance for high priority processes because they may compete less with other processes that get fewer cores. Now that I mention that, I'll probably give Slack a single core.

wmf 8y ago

IBM seems to have no official statement about whether z is vulnerable to Spectre but Power7/8/9 are/were definitely affected. Fujitsu SPARC is also vulnerable but interestingly Oracle SPARC is not. If Alpha, MIPS, or PA-RISC still existed I would expect most of them to be vulnerable as well. Are there specific hardware mechanisms in "real" server processors that can provide high performance without side channels? What are they?

nickpsecurity 8y ago
I wouldn't trust them. One might mitigate a bit using the classic patterns against side channels: randomization and masking. I came up with an idea for randomizing execution at CPU level but the person that beat me to it patented it. Possibly something like ARINC partitioning combined with randomization plus operations similar to those that process secrets, but process fake data. One of the simplest methods, though, is focusing the leak-proofing on the barrier between partitions handling secrets and everything else (esp w/ comms capability). Then, you just make sure you have trusted, hard-to-hack code on as much of the system as possible. No web browsers and such. Safe, system language with pointer and overflow protections along with performance hit that comes with. Otherwise, back to physical separation. I used that with KVM switch back in the day.
int_19h 8y ago
MIPS still exists, it's not uncommon in cheap routers. Here's their statement on vulnerabilities: https://www.mips.com/blog/mips-response-on-speculative-execution-and-side-channel-vulnerabilities/ https://www.mips.com/blog/mips-response-on-speculative-execu...
- rbanffy 8y ago
  In order to be vulnerable to Spectre, it needs out of order speculative execution. Not many low end CPUs do that.
rbanffy 8y ago
> high performance without side channels? What are they? One I can think of is cache partitioning by process id and security context. Not sure any CPU implements that. We can also use cpusets to assign processes to physical cores or sockets, limiting how much opportunity you have to see what other processes are doing. This can even increase performance for high priority processes because they may compete less with other processes that get fewer cores. Now that I mention that, I'll probably give Slack a single core.