Unofficially, it's very comparable to the MIPS architecture, but (much like e.g. the Alpha) it avoids some of the issues in MIPS that make it less usable for "h

Unofficially, it's very comparable to the MIPS architecture, but (much like e.g. the Alpha) it avoids some of the issues in MIPS that make it less usable for "high-performance" implementations. The extensibility is a fairly novel feature, as is the approach it uses for compressed, 16-bit instructions (a "clean" alternate-encoding for a subset of the same 32-bit instructions, not a new instruction set). Furthermore the instruction format uses some tricks that simplify decoding in hardware, although they do make a pure software implementation a bit harder. The upcoming V (vector processing) extension also chooses an approach that (while far from novel) hasn't seen much use recently, but will probably work better than the usual sort of SIMD for most use cases. It's worth mentioning the "privileged" architecture as well, as it benefits hugely from being a from-scratch design; it's a lot simpler than its equivalent in most other architectures, and it will probably support things like virtualization in a rather straightforward way.