I am definitely not an expert in CPU architecture, but I'll give it a shot. Generally I would say the main differences are: the whole RISC vs CISC argument, ho

I am definitely not an expert in CPU architecture, but I'll give it a shot. Generally I would say the main differences are: the whole RISC vs CISC argument, how future extensions work and how complicated decoding/encoding instructions is. I'm not going to go into RISC vs CISC as that has been constantly fought over and I am not qualified to have a substantiated position. The extension system for RISC-V is the biggest area where I think RISC-V excels. There is a very simple base instruction set which has things like loads/stores, addition, and branches. Then more complicated instructions such as multiplication, floating point, atomics, etc are all extensions which have a well defined structure and there is dedicated room for more standard extensions and custom ones. The technical advantage of this is that really cheap CPUs can support a tiny fraction of what big ones do, but still fit into the same mold as the big ones. Any custom instructions for a specific product can just be a custom instruction. Additionally, if an extension becomes useless in the future, just don't include it in future chips. If this has caught your attention, check out the specification [0]. IIRC, the decoding and encoding of RISC-V is dramatically simpler than x86 and ARM as it has only a normal 32 instruction format, a compressed 16 bit one and a large one (I think 128 bit). Importantly the non-default sizes are optional. MIPS has a simpler format, but takes slightly more silicon to decode (because its more human readable). I don't know any good references off the top of my head though, but I suspect searching for risc-v on HN is probably a good bet to find discussion of pros and cons. [0]: https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf https://content.riscv.org/wp-content/uploads/2017/05/riscv-s...