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Apart from the openness/freedom aspect, can anyone summarize the pros and cons of RISC-V from a technical perspective in comparison to other major ISAs, e.g. x8

Apart from the openness/freedom aspect, can anyone summarize the pros and cons of RISC-V from a technical perspective in comparison to other major ISAs, e.g. x86, ARM, MIPs? Or point to some resources discussing the matter?

deleted 8y ago
[deleted]
thethirdone 8y ago
I am definitely not an expert in CPU architecture, but I'll give it a shot. Generally I would say the main differences are: the whole RISC vs CISC argument, how future extensions work and how complicated decoding/encoding instructions is. I'm not going to go into RISC vs CISC as that has been constantly fought over and I am not qualified to have a substantiated position. The extension system for RISC-V is the biggest area where I think RISC-V excels. There is a very simple base instruction set which has things like loads/stores, addition, and branches. Then more complicated instructions such as multiplication, floating point, atomics, etc are all extensions which have a well defined structure and there is dedicated room for more standard extensions and custom ones. The technical advantage of this is that really cheap CPUs can support a tiny fraction of what big ones do, but still fit into the same mold as the big ones. Any custom instructions for a specific product can just be a custom instruction. Additionally, if an extension becomes useless in the future, just don't include it in future chips. If this has caught your attention, check out the specification [0]. IIRC, the decoding and encoding of RISC-V is dramatically simpler than x86 and ARM as it has only a normal 32 instruction format, a compressed 16 bit one and a large one (I think 128 bit). Importantly the non-default sizes are optional. MIPS has a simpler format, but takes slightly more silicon to decode (because its more human readable). I don't know any good references off the top of my head though, but I suspect searching for risc-v on HN is probably a good bet to find discussion of pros and cons. [0]: https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf https://content.riscv.org/wp-content/uploads/2017/05/riscv-s...
0815test 8y ago
Unofficially, it's very comparable to the MIPS architecture, but (much like e.g. the Alpha) it avoids some of the issues in MIPS that make it less usable for "high-performance" implementations. The extensibility is a fairly novel feature, as is the approach it uses for compressed, 16-bit instructions (a "clean" alternate-encoding for a subset of the same 32-bit instructions, not a new instruction set). Furthermore the instruction format uses some tricks that simplify decoding in hardware, although they do make a pure software implementation a bit harder. The upcoming V (vector processing) extension also chooses an approach that (while far from novel) hasn't seen much use recently, but will probably work better than the usual sort of SIMD for most use cases. It's worth mentioning the "privileged" architecture as well, as it benefits hugely from being a from-scratch design; it's a lot simpler than its equivalent in most other architectures, and it will probably support things like virtualization in a rather straightforward way.
childintime 8y ago
I'd point to the RISC-V talks given by Krste Asanovic or Dave Patterson. Perhaps those from 2016 are best.

deleted 8y ago

[deleted]

thethirdone 8y ago

I am definitely not an expert in CPU architecture, but I'll give it a shot. Generally I would say the main differences are: the whole RISC vs CISC argument, how future extensions work and how complicated decoding/encoding instructions is. I'm not going to go into RISC vs CISC as that has been constantly fought over and I am not qualified to have a substantiated position. The extension system for RISC-V is the biggest area where I think RISC-V excels. There is a very simple base instruction set which has things like loads/stores, addition, and branches. Then more complicated instructions such as multiplication, floating point, atomics, etc are all extensions which have a well defined structure and there is dedicated room for more standard extensions and custom ones. The technical advantage of this is that really cheap CPUs can support a tiny fraction of what big ones do, but still fit into the same mold as the big ones. Any custom instructions for a specific product can just be a custom instruction. Additionally, if an extension becomes useless in the future, just don't include it in future chips. If this has caught your attention, check out the specification [0]. IIRC, the decoding and encoding of RISC-V is dramatically simpler than x86 and ARM as it has only a normal 32 instruction format, a compressed 16 bit one and a large one (I think 128 bit). Importantly the non-default sizes are optional. MIPS has a simpler format, but takes slightly more silicon to decode (because its more human readable). I don't know any good references off the top of my head though, but I suspect searching for risc-v on HN is probably a good bet to find discussion of pros and cons. [0]: https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf https://content.riscv.org/wp-content/uploads/2017/05/riscv-s...

0815test 8y ago

Unofficially, it's very comparable to the MIPS architecture, but (much like e.g. the Alpha) it avoids some of the issues in MIPS that make it less usable for "high-performance" implementations. The extensibility is a fairly novel feature, as is the approach it uses for compressed, 16-bit instructions (a "clean" alternate-encoding for a subset of the same 32-bit instructions, not a new instruction set). Furthermore the instruction format uses some tricks that simplify decoding in hardware, although they do make a pure software implementation a bit harder. The upcoming V (vector processing) extension also chooses an approach that (while far from novel) hasn't seen much use recently, but will probably work better than the usual sort of SIMD for most use cases. It's worth mentioning the "privileged" architecture as well, as it benefits hugely from being a from-scratch design; it's a lot simpler than its equivalent in most other architectures, and it will probably support things like virtualization in a rather straightforward way.

childintime 8y ago

I'd point to the RISC-V talks given by Krste Asanovic or Dave Patterson. Perhaps those from 2016 are best.