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Why would you rewrite from Verilog to VHDL? I've always heard that the latter is significantly less expressive than the former.
by fouric 8y ago
Why would you rewrite from Verilog to VHDL? I've always heard that the latter is significantly less expressive than the former.
- howerj 8y agoSimply because I wanted to. I prefer VHDL because that's what I was taught at university, but I don't do any HDL work professionally so don't take it as a particularly informed decision.
- TomVDB 8y agoI'm a huge Verilog fan, but VHDL has a bunch of higher level features that Verilog doesn't have. E.g. records, limited range integers, enum types etc. SystemVerilog added these kind of features much later. That said: there are a bunch of constructs where Verilog really shines, especially when it comes to bit twiddling. When you care about open source tool flows, it's no contest: Verilog is far ahead on that front. That's currently the deciding factor for me.
- bpye 8y agoIt would rock if someone wrote a VHDL frontend for Yosys. You could then use Yosys to convert to Verilog for use with all the other open source tools.
- teabee89 8y agoThere is a link in https://github.com/YosysHQ/yosys/wiki/VHDL-frontend-efforts https://github.com/YosysHQ/yosys/wiki/VHDL-frontend-efforts