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Note the source is in SystemVerilog and not Verilog.
by basementcat 8y ago
Note the source is in SystemVerilog and not Verilog.
- JoachimS 8y agoExactly. And that might limit the open/free tools to use. Though looking at the code, there isn't that many advances SV concepts being used. So converting to std 2001 Verilog accepted by many tools should be easy. I haven't tested, but Icarus Verilog should be able to handle the code.