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Author here. My reason to choose the A15 was because it was shown on the WD performance slide with a performance that's close to the SweRV. The target use cas
by tverbeure 8y ago
Author here.
My reason to choose the A15 was because it was shown on the WD performance slide with a performance that's close to the SweRV.
The target use cases of the SweRV are obviously very different from the A15 (lack of MMU, lack of Dcache, lack of floating point will indeed do that).
But I didn't expect that adding these features would have a significant impact on peak performance of a benchmark that can fit completely in a cache?
My comment about complexity is entirely about the core execution pipeline: OoO vs in-order, number of pipes, number of ALUs. Even there, the A15 is significantly more complex than the SweRV, yet it performs more or less the same in best case circumstances. I expected at least some benefits? Since that is not the case, I assume that this complexity helps for non-ideal use cases (which the SweRV will probably never experience.)
Edit: as _chris_ points out: OoO helps when you start missing the L1 hits.
- tyingq 8y agoMakes sense. It pops in my head because any RISCV story here usually gets flooded with people hoping for an affordable RISCV chip that will run Linux. I figured the comparison might spawn some false hope :)