That's not what RISC means. The fact that it's using a different microarchitecture on the inside doesn't in anyway eliminate the complexity and challenges that

That's not what RISC means. The fact that it's using a different microarchitecture on the inside doesn't in anyway eliminate the complexity and challenges that comes from the ISA, not least the complexity for the decoder and branch predictors. What Intel (and IBM's Z9) has demonstrated is that with enough enginering and silicon, you can still make complexity go fast. What RISC (like RISC-V and Aarch64) enables is the same kind of microarchitecture but with far far lower complexity (= time to market, design team, etc). Intel is still doing really well because the physical design (custom cells) is hard and takes teams that are hard to come by. Things are very interesting right now and for the next few years.