2 ms·
Its not meaningful to distinguish Thumb and Thumb2 - Thumb2 was just a bunch of new instructions added to Thumb. A typical ARMv8-A processor needs to decode th
by repiret 8y ago
Its not meaningful to distinguish Thumb and Thumb2 - Thumb2 was just a bunch of new instructions added to Thumb.
A typical ARMv8-A processor needs to decode the A64, A32 and T32 instruction sets, but that doesn't strike me as a significant burden. A32 and T32 are essentially just different encodings of the same instruction set - there are very few A32 or T32 instructions that don't have an equal in the other instruction set. A64 has more and wider registers, but is otherwise broadly similar in capabilities. I would expect that most ARMv8-A implementations unify the three instruction sets very early in the decoding process.
Retaining the system level aspects of AArch32 strikes me as more expensive, especially support for short page tables, the subtly different system register layout, the more complex relationship between PSTATE.M and the security state, and the banked system registers between the secure and non-secure states. I'm surprised ARM-designed cores haven't pushed harder to eliminate AArch32 at the higher exception levels (although I'm aware of some cores designed by ARM Architecture licensees that do so). Perhaps that ARM has retained AArch32 all the way up to EL3 is evidence that they believe doing so isn't very expensive.
- als0 8y ago> I'm surprised ARM-designed cores haven't pushed harder to eliminate AArch32 at the higher exception levels It seems like they are very slowly phasing it out and heading to 64-bit only. A32 ISA is only supported in userspace mode (EL0) on the Cortex-A76[1]. [1] https://www.theregister.co.uk/2018/05/31/arm_cortex_a76/ https://www.theregister.co.uk/2018/05/31/arm_cortex_a76/