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A Superscalar Out-of-Order x86 Soft Processor for FPGA (2017)
- hak8or 8y agoHow is this legally handled considering amd owns x86-64 and Intel owns x86? As long as it's not used in commercial settings, will they pretend not to see it while users are in a legally gray area?
- wk_end 8y agoThis is x86 only, and a quick skim of the dissertation suggests that it doesn't implement any post-P6 (Pentium Pro) instructions. The P6 is 24 years old now so presumably all patents are expired?
- userbinator 8y agoThe last time I looked, the MMX patents were close to expiry too, and by now they might be.
- Const-me 8y agoMMX is from P5. P6 supports MMX and later revisions SSE 1. The next one after P6 is NetBurst, it introduced SSE2 and later revisions SSE3.
- Skunkleton 8y agoI am by no means an expert in digital design (I have only worked with them as a SWE), but it seems to me that the use cases for a high performance soft processor are pretty few and far between. After all, if you want a fast processor you can get a hard processor with excellent performance/support for less than the FPGA fabric likely cost. Still a cool piece of tech though.
- monocasa 8y agoSection 1.1 makes a pretty good argument in favor.
- Skunkleton 8y agoWhat I am trying to say is that FPGA fabric is expensive, and at some point if you use too much, then it will push you to a new part. Most of the time I would guess it to be cheaper to have a separate processor for more intensive tasks. Of course if you have some IP that is partially implemented in a soft core, then it might not be practical to offload it to an external cpu.
- FullyFunctional 8y agoActually, I think FPGAs are amazingly cheap compared to what it would cost you to fab a chip of similar specs. A leading-edge FPGA will get you near-leading edge DSPs, memory blocks, SerDes, etc. What you _don't_ get is the frequency of a custom part for the full design (this is the FPGA overhead). Simple RISC softcores run at 200-400 MHz in modern parts. Couple this with custom softcore accelerators and you can get very performant designs. The biggest issue with deploying FPGAs however is that it's much harder to design for, especially dealing with hard blocks, like memory controllers and PCIe.
- andrewf 8y agoAre there detailed writeups of people building these things into their systems? (Something like https://blog.cloudflare.com/building-fast-interpreters-in-rust/ https://blog.cloudflare.com/building-fast-interpreters-in-ru... but for FPGAs instead of Rust).
- bogomipz 8y ago>"Couple this with custom softcore accelerators and you can get very performant designs." Can you elaborate on what these softcore accelerators are or how they work? Might you have any links?
- basementcat 8y agoFrom section 6.8 (p. 69) "Note that the decoder’s microarchitecture design is complete, including the branch predictor design and micro-op sequences for nearly every x86 instruction and behaviour. Our circuit implementation is less complete than our microarchitecture design (implemented as a detailed pipeline simulation)" Still an impressive work.
- userbinator 8y agoOur microarchitecture achieves 2.7 times the per-clock performance of a performance-tuned Nios II/f, Alteraâ s fastest (RISC-like, single-issue, pipelined) soft processor, and 0.8 times the frequency, for a total performance improvement of 2.2 times. It'd be very interesting to compare this to RISC-V.
- pcwalton 8y agoNote that this the Nios II/f is an in-order CPU, while this is a superscalar CPU. A more relevant benchmark would be the superscalar dual-issue ARM Cortex-A9, illustrated in figure 13.4. It's about the same performance as that one if you average all the benchmarks. In theory, RISC-V should be at about the same performance as ARMv8 (note that Cortex-A9 is ARMv7): https://news.ycombinator.com/item?id=15343287 https://news.ycombinator.com/item?id=15343287
- snvzz 8y ago>In theory, RISC-V should be at about the same performance as ARMv8 Or POWER9, the cpu with the fastest IPC. And it's RISC. There's nothing to prevent RISC-V ISA from getting high performance implementations.
- snvzz 8y ago>It'd be very interesting to compare this to RISC-V. BOOM was close to ivy bridge performance in 2016.