3 ms·

The biggest difference between x86 and ARM for a big out-of-order machine is probably the much stronger memory ordering guarantees that x86 provides. There are

The biggest difference between x86 and ARM for a big out-of-order machine is probably the much stronger memory ordering guarantees that x86 provides. There are good points to be made on either side of that but it's clearly a very important consideration. The second biggest difference is that, in a big OoO core, the cost of decoding the instruction stream is trivial on ARM as opposed to merely small on x86. Something like 5% of the cores power budget on a modern x86, I think? One upshot of that is that on Intel chips the decode stage is balanced with the overall execution width so that they are only seldom decode limited. Whereas the attitude on high end ARM chips is that you might as well just throw in more decoders than you think you need so you can stop worrying about it. But overall ARM has traditionally been the CISCiest of the RISC architectures and x86 has been the RISCiest of the CISC architectures,[1] making me think they might have both ended up successful by being at a sort of happy medium. [1]https://userpages.umbc.edu/~vijay/mashey.on.risc.html https://userpages.umbc.edu/~vijay/mashey.on.risc.html

userbinator 8y ago
x86 has been the RISCiest of the CISC architectures I agree completely if you mean "RISCiest" as in the complexity of decoding instructions. Look at the opcode map of a VAX, for example --- instructions were simply added where they fit, so there's no easily discernable pattern in the bits of the first opcode byte. x86 has an octal structure to its instructions[1] and the first quarter of the opcode map (000 through 077 octal) contains nearly all the commonly used ALU operations. The 8086 along with the Z80 and its predecessors had to be implemented on a single chip, which put constraints on how complex its instruction encoding could be, which could explain why a regular structure (but not fixed length) was adopted instead of a more "true CISC" way of making every instruction opcode arbitrarily increasing and microcoding everything. [1] https://news.ycombinator.com/item?id=9322723 https://news.ycombinator.com/item?id=9322723

userbinator 8y ago

x86 has been the RISCiest of the CISC architectures I agree completely if you mean "RISCiest" as in the complexity of decoding instructions. Look at the opcode map of a VAX, for example --- instructions were simply added where they fit, so there's no easily discernable pattern in the bits of the first opcode byte. x86 has an octal structure to its instructions[1] and the first quarter of the opcode map (000 through 077 octal) contains nearly all the commonly used ALU operations. The 8086 along with the Z80 and its predecessors had to be implemented on a single chip, which put constraints on how complex its instruction encoding could be, which could explain why a regular structure (but not fixed length) was adopted instead of a more "true CISC" way of making every instruction opcode arbitrarily increasing and microcoding everything. [1] https://news.ycombinator.com/item?id=9322723 https://news.ycombinator.com/item?id=9322723