3 ms·
I'm actually sort of surprised that ARM doesn't do that. Given that they have Thumb sitting there for them to use and given that i-cache pressure is an importa
by Symmetry 8y ago
I'm actually sort of surprised that ARM doesn't do that. Given that they have Thumb sitting there for them to use and given that i-cache pressure is an important consideration sometimes I would tend to assume it would be a no-brainer. Given that ARM's architects know more about this than I do I have to conclude that there are more disadvantages to even simple variable length instruction encodings than I would assume.
Has anyone made a R64GC out of order core yet?
- monocasa 8y agohttps://github.com/riscv-boom/riscv-boom https://github.com/riscv-boom/riscv-boom Open source, and taped out.
- Symmetry 8y agoOh, nice! I'd last seen the original presentation when BOOM was still going to use just 32 bit instructions. Section 2.2 from here[1] goes into some details on the challenges of using compressed instructions and how they deal with them. https://docs.boom-core.org/en/latest/sections/instruction-fetch-stage.html https://docs.boom-core.org/en/latest/sections/instruction-fe...
- jabl 8y agoInteresting, though RVC support is pretty new, seems it was merged just a little over a month ago: https://github.com/riscv-boom/riscv-boom/pull/141 https://github.com/riscv-boom/riscv-boom/pull/141 I'd guess the taped out versions were prior to this improvement.